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Zhu Lin
Advisors: Prawat Nagvajara, Ph.D.
Abstract:
In the on-line assessment of an electrical power grid to assure reliable operation, the state estimator provides a real-time status of the grid. It estimates the node voltages (states) based on redundant measurement data being transmitted from the Supervisory Control and Data Acquisition (SCADA) system via networks and telemetry. Consequently, the state estimation requires high-performance computing, which involves sparse matrices orthogonal factorization (e.g., Givens rotation). We propose an alternative high-performance computing platform which comprises a host computer interconnected to a Field Programmable Gate Array (FPGA) via a PCI-Express bus. Algorithm-specific hardware can be programmed onto the FPGA to accelerate the computation. The goal is to analyze the performance of the proposed platform in comparison to the traditional processor, e.g., Pentium processor, for power system state estimation.
We developed two hardware performance models of Givens rotation algorithms: columned-oriented and row-oriented; and analyzed their performance (in seconds) based on the clock rate, the estimated total number of clock cycles of the hardware on the FPGA and the host/FPGA data transfer time. The predicted performance obtained from the state estimation of benchmark power grids (118-bus and 1648-bus systems) shows that the row-oriented Givens algorithm-specific hardware can provide 25-fold speedup over the software program of the same state estimation algorithm running on Pentium M 1.7GHz. This result indicates that algorithm-specific hardware on FPGA may provide a cost-effective solution to high-performance state estimation.
Friday, June 1st, 2007 at 10 a.m.
Curtis Hall, Room 053B
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