Experiment 4 - Inverter Characteristics

Written by S.S Mehta, W.T. Yeung, C.F. Yeung, C. Hsiung, and R.T.Howe for UC Berkeley course EE 105

Modified by K. Scoles for Drexel University course ECE-E433

1.0 Objective

In this experiment, you will determine the voltage transfer characteristic (VTC) of several different MOS inverter topologies by graphing load lines and by performing actual measurements. In addition, you will be calculating and measuring the voltage gain and comparing the propagation delays of the different inverters. The key concepts introduced in this laboratory are:

• Using loadline method to find the VTC
• Comparison of different inverter topologies
• Comparison of propagation delays for different inverter topologies
• Comparison of voltage gains for different inverter topologies

2.0 Prelab

• Read Geiger, et al, "VLSI Design Techniques for Analog and Digital Circuits" - Chapters 7.3, 7.5, 7.8 or Howe & Sodoni: "Microelectronics, An Integrated Approach" - Chapters 5.1 - 5.4
• Using the I-V characteristics for the NMOS transistor (W = 46.5 um L= 1.5 um) measured in Experiment 1, draw in the loadline for a 1 kohm resistor. Using loadline analysis, determine (and plot) the voltage transfer characteristic of this inverter.
• Using SPICE, determine the VTC for the CMOS inverter shown in figure 2. Use the parameters derived from Experiment 1 measurements on the PMOS and NMOS transistors (VTO, KP, LAMBDA). Also determine the simulated rise time, fall time, and stage delays if this inverter is driven by a 5V 2 kHz square wave..

3.0 Procedure

Hardware Used

• Philips PM2812 2-channel dc power supply with GPIB control
  • This supply has a "read-back" capability, meaning the voltage at the terminals and the current being drawn can be read over the GPIB bus.
• Fluke 8840A Multimeter with GPIB control
  • This meter is used to read inverter output voltage
• Macintosh IIfx computer with National Instruments GPIB Controller card
• MicroLinear Chip Set, "EE105 Components", designed at UC Berkeley and distributed by Electronic School Supply

Software

• National Instruments LabVIEW software and custom Virtual Instruments (Exp4A.vi)
• MicroSim PSpice
• Microsoft Excel

3.1 Resistively-loaded NMOS Inverter

1. Connect the NMOS inverter shown in figure 1. Let R_L=1 kohm. Don't forget to short the source (pin 5) to ground (pin 14).

FIGURE 1. Resistively loaded NMOS inverter. The NMOS transistor is found on Lab Chip 1.

2. Use the Exp4a.vi software to set Vdd on Ch1 of the DC power supply, and a ramped input voltage (0 to 5 V) on Ch2 of the supply. The Fluke digital multimeter is used to determine the voltage at the output. The resulting voltage transfer characteristic is plotted from the data. Comment on the important points of the graph such as V_OH, V_OL, V_M, noise margins, etc.

3. From the slope of the transition region, determine the voltage gain A_v. How does it compare with the theoretical value?

4. Attach a load capacitance of 100 nF to the output node. Apply a 200 Hz 0 to 5 volt square wave to the input of the inverter. Set the DC offset to be 2.5V. Use the oscilloscope to plot v_IN and v_OUT and produce a hard copy. Measure the rise and fall times, t_r and t_f, and propagation delays, t_plh and t_phl, of the inverter.

• Make sure that the DC offset on the generator is set. Adjust the frequency on the generator if the circuit cannot respond fast enough. The specification at 200 Hz is by no mean set in stone.
• You can to used the delayed-time setting on the scope to get more accurate measurements of the propagation delay time

.

5. Perform a DC analysis with SPICE to find the VTC. Perform a transient analysis to find the propagation delay. How does simulation compare with experiment? Plot the simulated and measured results on the same curve.

3.2 CMOS Inverter

3.2.1 DC Characteristics

1. Place the Lab Chip 2 in a protoboard. Figure 2 shows the pinouts of the CMOS inverters you will be testing.

FIGURE 2. Small CMOS inverter. The CMOS inverter is found on Lab Chip 2.

2. Note the channel definitions and connect the appropriate channels. Connect Channel 1 of the Philips supply between Vdd and GND. Connect Channel 2 between V_in and GND. Measure the voltage between V_out and ground with the multimeter. Use the Exp4a.vi software to run the measurement.

3. Note the VTC of this inverter. Using the cursors, find the slope of the line through the transition region and find the gain of the inverter.

FIGURE 3. Sample VTC for CMOS inverter

4. Save your VTC data in a spreadsheet file. Compare it to the SPICE simulation done in the Prelab.

3.2.2 Transient Characteristics

1. Place the Lab chip 2 on your breadboard. Connect a 100nF capacitor at the output V_out.
2. Apply a 2 kHz 0 to 5 volt square wave to the input of the inverter. Set the DC offset to be 2.5V. Use the oscilloscope to plot v_IN and v_OUT Measure the rise and fall times, t_r and t_f, and propagation delays, t_plh and t_phl, of the inverter. Also compare the delay time with the delay time of the inverter with resistive load.

4.0 Optional Experiments

4.1 Enhancement Load NMOS Inverter

FIGURE 4. Enhancement Load NMOS Inverter. Both NMOS trasistors are on Lab Chip 1.

1. Place the Lab Chip 1 on your breadboard. Construct the inverter as above. Connect a 100 nF Capacitor at the output Vout.
2. Apply a 2 kHz 0 to 5 volt square wave to the input of the inverter. Set the DC offset to be 2.5 V. Use the oscilloscope to plot v_IN and v_OUT. Measure the propagation delays t_plh and t_phl of the inverter.
3. Measure the rise and fall times, t_r and t_f, and propagation delays, t_plh and t_phl, of the inverter. How do these numbers compare with those for the other inverters?

4.2 Pseudo NMOS Inverter

Repeat the above experiment for the following inverter. Apply 1 volt to the gate of the PMOS. Also, apply a 500 Hz 0 to 5 volt square wave to the input of the inverter. The PMOS can be found on Lab Chip 2 while the NMOS is from Lab Chip 1.

FIGURE 5. Pseudo NMOS Inverter

5.0 Appendix

The CMOS inverter layout shown below. Note that this is the layout for the CMOS inverter in Lab Chip 2.

FIGURE 6. Layout for CMOS Inverter