Experiment 5 - Digital Circuits

Developed by S.M. Mehta, W.T. Yeung, Charles Hsiung, and R.T. Howe for UC Berkeley course EE 105

Modified by K.J. Scoles for Drexel University course ECE-E433

1.0 Objective

In this experiment, you will examine several different CMOS digital circuits. You will test the functionality of the digital logic circuits and compare the propagation delays of each. In addition, you will examine the properties of a ring oscillator. The key concepts introduced in this lab are:

The functionality of digital circuits
The different propagation delays associated with different transitions
Using the ring oscillator to measure the switching speed

2.0 Prelab

Read H& S: Chapter 5.5 - 5.6

Write the truth tables and Karnaugh maps for the following Boolean equations:

Draw CMOS circuits that implement these equations
Write the Boolean equations and the truth tables for the circuits in figure 1. What logic functions do they implement?

Figure 1. CMOS Digital Circuits

3.0 Procedure

3.1 Determination of Logic

1. The figure below shows a "mystery" 2 input logic function on Lab Chip 3. Place the chip in your breadboard and connect the power and ground pin.

Figure 2. Unknown CMOS Logic Circuit on CA122005BPG

2. Construct the truth table for this circuit using all possible combinations for A and B.

Lab Tip: Use the Buslines for GND and V_DD for the inputs A and B. This will minimize the number of wires and cables on your board.

3. Write down the Boolean equation which describes the function of the circuit. What does this circuit do?

4. Place a 100 nF load on the output. Connect inputs A and B together. Prepare your signal generator to provide a 0 to 5 V, 1 kHz squarewave output (watch your DC offset). Connect the squarewave to the combined input. Measure t_plh and t_phl. Disconnect input B from A and connect it to ground. Measure t_phl and t_plh. Are there any differences in the delay times? What explanations can you offer?

3.2 NAND gate

1. Connect the NAND gate shown in figure 3. The NAND gate is found on Lab Chip 3.

Figure 3. NAND Gate on Lab Chip 3. All transistors have W = 93 um, L = 1.5 um.

2. Construct the truth table for this circuit using all possible combinations for A and B.

3. Write down the Boolean equation which describes the NAND gate. Does the circuit perform the required function?

4. Place a 100 nF load on the output. Connect inputs A and B together. Connect a 0 to 5 volt square wave with a frequency of 1 kHz to the combined input. Measure t_plh and t_phl. Disconnect input B from A and connect it to 5 volts. Measure t_phl and t_plh. Now connect A to 5 volts and have B switch from 0 to 5 volts. Measure t_phl and t_plh. Are there any differences in the delay times? What explanations can you offer?

3.3 143 Stage Ring Oscillator

1. Connect the ring oscillator as shown below. The ring oscillator is found on Lab Chip 3. Note that the ring oscillator has its own supply pin (PIN 10).

Figure 4. Ring Oscillator Circuit

Connecting pins 28 and 10 together makes for a cleaner measurement. Vary the supply from 0 to 5 volts and measure the frequency vs. V_DD. Make a graph of the frequency versus the supply voltage. What sort of dependence does it have? Determine the switching speed of each inverter from the basic relationship between t_p, the number of inverters, and the frequency of the ring oscillator. Also, determine the load capacitance per stage using the value of K_n found before.

4.0 Optional Experiment

4.1 Dynamic Logic

1. Connect the dynamic logic circuit shown in figure 5. Use the DIP switch for the four inputs. Attach a load capacitance of 10 pF to the output node.

2. Write V_out as a function of A, B, C and phi. Connect all four inputs to switches. Normally, phi is connected to a clock, but in this lab you will clock the circuit manually. In precharge mode phi=0 (0V) and in evaluate mode phi=1 (5V). Change the logic levels of A, B and C and check if the voltage at V_OUT is changing. Why shouldn't it change?

3. Let A=0, B=1 and C=0 -- in evaluate mode, switch phi must be set to high first. If the output has a path to ground it will pull low. Check this by switching A high.

FIGURE 5. Dynamic Logic Circuit found on Lab Chip 3. All transistors have W = 93 um, L = 1.5 um.