Review of Karnaugh Maps
Application to MOS Digital Design
Two-Input NAND Gate
Symbol
Truth Table
A |
B |
Q |
0 |
0 |
1 |
0 |
1 |
1 |
1 |
0 |
1 |
1 |
1 |
0 |
The Karnaugh map for this or any logic function can be used to determine the transistor schematic. The K-map and the technology choice (NMOS or CMOS) determine the number, type (PMOS or NMOS) and connectivity of the transistors.
Karnaugh Map
B | |||
0 |
1 | ||
A |
0 |
1 |
1 |
1 |
1 |
0 | |
You can think of the MOS logic gate as a pull-up block connected between Vdd and output, and a pull-down block connected between output and ground. The pull-up block consists of a single NMOS depletion transistor for NMOS gates and a p-transistor network for CMOS gates. The pull-down block consists of a NMOS enhancement transistor network for each technology.
What part of the MOS gate determines the high (one) logic output? The pull-up. The ones from the K-map determine the CMOS p-block topology.
Step 1. Identify the "Ones" in the K-map
B | |||
0 |
1 | ||
A |
0 |
1 |
1 |
1 |
1 |
0 | |
If the inputs are A and B, where do Abar and Bbar come from? Since we are dealing with p-transistors, imagine that the "bubbles" on the p-transistor gates generate Abar and Bbar from A and B respectively.
The pull-down block, made up of n-transistors, permits the output to be pulled to ground (zero logic level) conditionally, depending on the inputs. The zeroes from the K-map determine the n-transistor topology.
Step 2. Identify the zeroes in the K-map
B | |||
0 |
1 | ||
A |
0 |
1 |
1 |
1 |
1 |
0 | |
Step 3. Build the N- and P-blocks
Rules:
+ OR function, transistors in parallel
* AND function, transistors in series
For the CMOS 2-input NAND gate, we have 2 p-transistors with inputs A and B in parallel, and 2 n-transistors with inputs A and B in series.
Transisor Schematic
